1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a manufacturing method of an array substrate for a liquid crystal display device having a color filter layer on a thin film transistor.
2. Discussion of the Related Art
A liquid crystal display (LCD) device is driven based on the optical anisotropy and polarization characteristics of a liquid crystal material. In general, the LCD device includes two substrates spaced apart and facing each other with a liquid crystal material layer interposed between the two substrates. Each of the substrates includes electrodes facing each other such that a voltage applied to each electrode induces an electric field between the electrodes perpendicular to the substrates. An alignment of liquid crystal molecules of the liquid crystal material layer changes by varying an intensity or direction of the applied electric field. Accordingly, the LCD device displays an image by varying light transmittance through the liquid crystal material layer in accordance with the arrangement of the liquid crystal molecules.
FIG. 1 is an expanded perspective view illustrating a related art LCD device. As shown in FIG. 1, the LCD device 11 includes an upper substrate 5, referred to as a color filter substrate, a lower substrate 22, referred to as an array substrate, and a liquid crystal material layer 14 interposed therebetween. On the upper substrate 5, a black matrix 6 and a color filter layer 8 are formed in a shape of an array matrix including a plurality of red (R), green (G), and blue (B) color filters surrounded by corresponding portions of the black matrix 6. Additionally, a common electrode 18 is formed on the upper substrate 5 to cover the color filter layer 8 and the black matrix 6.
On the lower substrate 22, a plurality of thin film transistors (TFTs) T are formed as an array matrix corresponding to the color filter layer 8. A plurality of gate lines 13 perpendicularly cross a plurality of data lines 15. The TFTs T are positioned such that each TFT T is located adjacent to an intersection of one of the gate lines 13 and one of the data lines 15. Furthermore, a plurality of pixel electrodes 17 are formed on a pixel region P defined by the gate lines 13 and the data lines 15 of the lower substrate 22. The pixel electrode 17 includes a transparent conductive material having high transmittance, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).
As further shown in FIG. 1, a storage capacitor CST is disposed in each pixel and connected in parallel to the pixel electrode 17 of the pixel. The storage capacitor CST includes a portion of the gate line 13 as a first capacitor electrode and a metal pattern 30 as a second capacitor electrode. Since the metal pattern 30 is connected to the pixel electrode 17 through a contact hole, the storage capacitor CST is electrically contacted to the pixel electrode 17. The metal pattern 30 may be made of the same material as the data line 15. When fabricating the LCD device 11 shown in FIG. 1, the upper substrate 5 is aligned with and attached to the lower substrate 22. In this process, the upper substrate 5 may be misaligned with the lower substrate 22 and light leakage may occur in the LCD device 11 due to an error margin in attaching the upper and lower substrate 5 and 22 together.
FIG. 2 is a cross-sectional view along the line II-II of FIG. 1 illustrating a pixel of the related art LCD device. As shown in FIG. 2, the related art LCD device includes the upper substrate 5, the lower substrate 22, and the liquid crystal layer 14. The upper and lower substrates 5 and 22 are spaced apart from each other, and the liquid crystal layer 14 is interposed therebetween.
A pixel region P, including a switching region S, and a storage region ST are defined on the lower substrate 22. A thin film transistor T is formed in the switching region S and includes a gate electrode 32, an active layer 34, a source electrode 36 and a drain electrode 38. A transparent pixel electrode 17 is formed in the pixel region P.
Referring to FIG. 1, the gate electrode 32 extends from the gate line 13 and the source electrode 36 extends from the data line 15. The gate, source, and drain electrodes 32, 36, and 38 are formed of a metallic material while the active layer 34 is formed of silicon. The pixel electrode 17 is formed of a transparent conducting material.
A storage capacitor CST is formed in the storage region ST and includes a portion of a gate line 13 as a first capacitor electrode and a metal pattern 30 as a second electrode. The metal pattern 30 has an island shape and overlaps this portion of the gate line 13. The metal pattern 30 contacts the pixel electrode 17.
A passivation layer 40 is formed on the thin film transistor T and the storage capacitor CST.
In FIG. 2, the upper substrate 5 is spaced apart from the lower substrate 22. On an inner surface of the upper substrate 5, a black matrix 6 is disposed in the position corresponding to the thin film transistor T, the gate line 13 and the data line 15. The black matrix 6 is formed on the entire surface of the upper substrate 5 and has openings corresponding to the pixel electrode 17 of the lower substrate 11, as shown in FIG. 1. The black matrix 6 prevents light leakage in the LCD device except for the portion for the pixel electrode 17. The black matrix 6 protects the thin film transistor T from the light such that the black matrix 6 prevents the thin film transistor T from generating a photo current. The color filter layer including color filters 8a, 8b and 8c is formed on the inner surface of the upper substrate 5 to cover the black matrix 6. Each of color filters 8a, 8b and 8c has one of the red, green, and blue colors and corresponds to one pixel region P where the pixel electrode 17 is located. A common electrode 18 formed of a transparent conductive material is disposed on the color filter layer 8 over the upper substrate 5.
As stated above, the lower substrate 22 and the upper substrate 5 are fabricated respectively and then attached to each other.
In the related art LCD device, each pixel electrode 17 corresponds to each color filter. Furthermore, to prevent cross-talk between the pixel electrode 17 and the gate and data lines 13 and 15, the pixel electrode 17 is spaced apart from the data line 15 by a distance A and from the gate line 13 by a distance C, as shown in FIG. 2. The open areas A and C between the pixel electrode 17 and the data and gate lines 15 and 13 cause light leakage in the LCD device. Typically, light leakage primarily occurs in the open areas A and C. However, the black matrix 6 formed on the upper substrate 5 should cover the open areas A and C. However, when arranging the upper substrate 5 with the lower substrate 22 or vice versa, a misalignment may occur between the upper substrate 5 and the lower substrate 22. Therefore, the black matrix 6 is extended to be sure that the black matrix still covers the open areas A and C. That is, the black matrix 6 is designed to provide an alignment margin to prevent light leakage. However, by extending the black matrix, an aperture ratio of the liquid crystal display device is reduced in as much as the alignment margin of the black matrix 6 increases. Moreover, if there are errors in the alignment margin of the black matrix 6, light leakage occurs in the open areas A and C, thereby deteriorating the image quality of the LCD device.
To solve the above problems, a liquid crystal display device having a color filter on thin film transistor (COT) structure has been suggested.
FIG. 3 is a plan view of an array substrate for a liquid crystal display device having a COT structure according to the related art.
In FIG. 3, a plurality of gate lines 52 are formed along a first direction on a substrate. The gate lines 52 are parallel to and spaced apart from each other. A plurality of data lines 68 are formed along a second direction perpendicular to the first direction. The data lines 68 are parallel to and spaced apart from each other. The data lines 68 cross the gate lines 52 to define a plurality of pixel regions P.
A gate pad 56 is formed at one end of each gate line 52, and a transparent gate pad terminal 94 covers the gate pad 56. A data pad 70 is formed at one end of each data line 68, and a transparent data pad terminal 96 covers the data pad 70.
A thin film transistor T is formed at each crossing of the gate and data lines 52 and 68. The thin film transistor T includes a gate electrode 54, a semiconductor layer 60, a source electrode 64 and a drain electrode 66. An extending portion 62 extending from the semiconductor layer 60 may be further formed under the data line 68 in order to improve the contact of the data line 68.
Each color filter 78a, 78b and 78c of a color filter layer is formed in each pixel region P. A black matrix 76 corresponds to the thin film transistor T. Additionally, the black matrix 76 may further include portions corresponding to the gate line 52 and the data line 68.
A metal pattern 72 of an island shape is formed over the gate line 52. The gate line 52 and the metal pattern 72 constitute a storage capacitor CST. The gate line 52 functions as a first electrode of the storage capacitor CST, and the metal pattern 72 functions as a second electrode of the storage capacitor CST. The storage capacitor CST may have various structures and positions.
A pixel electrode 92 is formed in each pixel region P. The pixel electrode 92 contacts the drain electrode 66 and the metal pattern 72.
In the above array substrate, since the color filter layer and the black matrix 76 are formed on the same substrate as the thin film transistor T and the pixel electrode 92, a portion as much as the alignment margin may be used for an aperture area to thereby increase an aperture ratio.
A manufacturing method of an array substrate for an LCD device having a COT structure according to the related art will be explained hereinafter with reference to attached drawings.
FIGS. 4A, 4B and 4C through FIGS. 8A, 8B and 8C illustrate a manufacturing method of an array substrate for an LCD device having a COT structure according to the related art.
FIGS. 4A, 4B and 4C illustrate a first mask process and a second mask process and correspond to cross-sections along the line IVA-IVA, IVB-IVB and IVC-IVC of FIG. 3, respectively.
In FIGS. 4A, 4B and 4C, a pixel region P, including a switching region S, a storage region ST, a gate pad region GP and a data pad region DP are defined on a substrate 50. A gate electrode 54 and a gate line 52 are formed on the substrate 50 by sequentially depositing and then patterning a metallic material through a first mask process. The gate electrode 54 corresponds to the switching region S, and a portion of the gate line 52 corresponds to the storage region ST. The gate line 52 has a gate pad 56 at one end thereof, and the gate pad 56 is disposed in the gate pad region GP. The metallic material includes aluminum (Al) or an aluminum alloy such as AlNd.
A gate insulating layer 58 is formed on a substantially entire surface of the substrate 50 including the gate electrode 54 and the gate line 52 thereon by depositing one or more selected from an inorganic insulating material group including silicon nitride (SiNX) and silicon oxide (SiO2).
A semiconductor layer 60 is formed on the gate insulating layer 58 over the gate electrode 54 by sequentially depositing and then patterning an intrinsic amorphous silicon layer and an impurity-doped amorphous silicon layer through a second mask process. The semiconductor layer 60 includes an active layer 60a of intrinsic amorphous silicon and an ohmic contact layer 60b of impurity-doped amorphous silicon. An extending portion 62 perpendicularly extending from the semiconductor layer 60 is also formed on the gate insulating layer 58. The extending portion 62 may be omitted.
FIGS. 5A, 5B and 5C illustrate a third mask process and correspond to cross-sections along the line IVA-IVA, IVB-IVB and IVC-IVC of FIG. 3, respectively.
In FIGS. 5A, 5B and 5C, a metallic material is deposited on the entire surface of the substrate 50 including the active layer 60a and the ohmic contact layer 60b thereon and then is patterned through a third mask process to form a source electrode 64, a drain electrode 66 and a data line 68. The source and drain electrodes 64 and 66 are spaced apart and are over the ohmic contact layer 60b. The data line 68 is connected to the source electrode 64. A data pad 70 is formed at one end of the data line 68 and is disposed in the data pad region DP. A metal pattern 72 of an island shape is formed over the gate line 52 in the storage region ST simultaneously with the source and drain electrodes 64 and 66.
Next, the ohmic contact layer 60b exposed between the source and drain electrodes 64 and 66 is removed, thereby exposing the active layer 60a. 
FIGS. 6A, 6B and 6C illustrate a fourth mask process and a fifth mask process and correspond to cross-sections along the line IVA-IVA, IVB-IVB and IVC-IVC of FIG. 3, respectively.
In FIGS. 6A, 6B and 6C, a passivation layer 74 is formed on the entire surface of the substrate 50 including the source and drain electrodes 64 and 66 and the data line 68 thereon by depositing one selected from an inorganic insulating material group including silicon nitride (SiNX) and silicon oxide (SiO2).
A black matrix 76 is formed on the passivation layer 74 by sequentially coating and then patterning black resin through a fourth mask process. The black matrix 76 corresponds to the source and drain electrodes 64 and 66 and the exposed active layer 60a. The black matrix 76 may further include portions corresponding to the gate line 52 and the data line 68.
Next, a color filter layer, for example a green color filter 78b, is formed on the passivation layer 74 in the pixel region P by sequentially coating and then patterning color resin through a fifth mask process. Although not shown in the drawings, red and blue color filters are formed through the same process as the green color filter 78b. 
FIGS. 7A, 7B and 7C illustrate a sixth mask process and correspond to cross-sections along the line IVA-IVA, IVB-IVB and IVC-IVC of FIG. 3, respectively.
In FIGS. 7A, 7B and 7C, a planarization layer 80 is formed on the entire surface of the substrate 50 including the color filter layer 78b by coating one of benzocyclobutene (BCB) and acrylic resin. The planarization layer 80 is patterned through a sixth mask process to thereby form a drain contact hole 82, a storage contact hole 84, a gate pad contact hole 86 and a data pad contact hole 88. The drain contact hole 82 exposes the drain electrode 66; the storage contact hole 84 exposes the metal pattern 72; the gate pad contact hole 86 exposes the gate pad 56; and the data pad contact hole 88 exposes the data pad 70.
FIGS. 8A, 8B and 8C illustrate a seventh mask process and correspond to cross-sections along the line IVA-IVA, IVB-IVB and IVC-IVC of FIG. 3, respectively.
In FIGS. 8A, 8B and 8C, a pixel electrode 92, a gate pad terminal 94 and a data pad terminal 96 are formed on the substrate 50 including the planarization layer 80 thereon by sequentially depositing and then patterning one selected from a transparent conductive material group including indium tin oxide (ITO) and indium zinc oxide (IZO) through a seventh mask process. The pixel electrode 92 contacts the drain electrode 66, and the metal pattern 72 and is disposed in the pixel region P. The gate pad terminal 94 contacts the gate pad 56, and the data pad terminal 96 contacts the data pad 70.
Therefore, the array substrate for the liquid crystal display device of the related art may be fabricated through seven-mask processes.
However, since each of the mask processes includes several steps of cleaning, coating a photo-resist layer, exposing through a mask, developing the photoresist layer, and etching, the entire processes are very complicated and expensive. Therefore, how to reduce fabricating time and costs by simplifying the processes is an important issue to be resolved.